sysroot =./././Versal_Platform_Creation/Tutorial-VCK190_Custom/ref_files/step2_petalinux/build/petalinux/images/linux/sdk/sysroots/aarch64-xilinx-linux \ There are additional net objects to hook up the RTL kernel to the rest of the platform object.įor more information on RTL kernels in the AI Engine see: Design Flow Using RTL Programmable Logic.Ĭompile the graph using the following command:Īarch64-linux-gnu-g++ -Wall -c -std =c++14 -Wno-int-to-pointer-cast \ The simulation::platform object now has the two extra PLIO interfaces. These are to hook up to the polar_clip RTL kernel. Two additional PLIO objects ai_to_pl and pl_to_ai are added. sink ) #ifdef _AIESIM_ int main ( int argc, char ** argv ) #endif in ) // Additional nets to the RTL Kernel connect net1 ( clipgraph.
#include "graph.h" PLIO * in0 = new PLIO ( "DataIn1", adf :: plio_32_bits, "data/input.txt" ) // RTL Kernel PLIO PLIO * ai_to_pl = new PLIO ( "clip_in", adf :: plio_32_bits, "data/output.txt" ) PLIO * pl_to_ai = new PLIO ( "clip_out", adf :: plio_32_bits, "data/input2.txt" ) PLIO * out0 = new PLIO ( "DataOut1", adf :: plio_32_bits, "data/output.txt" ) // RTL Kernel Addition to the platform simulation :: platform platform ( in0, pl_to_ai, out0, ai_to_pl ) clipped clipgraph connect net0 ( platform.
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